This guide covers the formulation, selection, and use of chemical solutions developed to reveal structural defects in silicon wafers.

Sample preparation, temperature control, etching technique, and choice of etchant are all key factors in the successful use of an etching method. This guide provides information for several etching solutions and provides guidance for the user to select according to the need. Illustrations of results obtained with these etching solutions are provided in Figures 1–32.

This guide is intended for use with other practices and test methods. SEMI MF1725 and SEMI MF1726 are practices for analysis of crystallographic perfection of silicon ingots and wafers, respectively, utilizing etching solutions found in this guide, and followed by counting in accordance with the test method SEMI MF1810. SEMI MF1727 defines the procedures for oxidation of the wafer prior to etching, if that is required to expose the defect structures of interest. JIS H 0609 is a test method that covers the entire process of determining crystalline defects in silicon wafers.

Both this guide and JIS H 0609 emphasize the use of etching solutions that do not contain chromic acid, which is biologically and ecologically very hazardous (see Section 7.6). Because of the hazardous nature of chrome containing etchants, the use of chromic acid containing etchants is prohibited in some jurisdictions located in various parts of the world.

NOTE 1: See Related Information 1 for a discussion of the relationships between this guide and JIS H-0609.

NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the user of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use.

Purpose

Structural defects formed in the bulk of a silicon wafer during its growth or induced by electronic device processing can affect the performance of the circuitry fabricated on that wafer. These defects take the form of dislocations, slip, stacking faults, shallow pits, or precipitates.

The exposure of the various defects found on or in a silicon wafer is often the first critical step in evaluating wafer quality or initiating failure analysis of an errant device structure. Etching often accomplishes this task. This guide provides information on the selection and application of appropriate etching solutions.