This guide addresses reporting the characterization of nanotopography surface features found on wafer surfaces. Nanotopography is the non-planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area (FQA). Typical examples include dips, bumps or waves on the wafer surface that vary in peak to valley height from a few nanometers to a several hundred nanometers.

This guide provides a framework for communicating specific values limiting feature levels and/or densities as agreed upon between suppliers and users. It is intended to apply to polished wafers as specified in SEMI M1.

Although nanotopography measurements have not been needed for 0.25 µm generation devices, they are expected to be required for smaller feature sizes to meet CMP requirements. Nanotopography on a wafer surface prior to CMP processes can result in variations in post-CMP dielectric thickness with potential negative consequences for circuit performance and yield; features as small as 20 nm (peak to valley) can result in post CMP discoloration of dielectrics as a result of local thickness variation of the remaining dielectric.¹ Height variations over specified distances (determined by CMP issues and/or lithography systems) need to be properly controlled to assure that wafers are acceptable for selected process steps. In the case of CMP, the issue is control of film thickness variation introduced by nanotopography. The metrology industry is building tools that will measure and map surface features at nanotopography amplitudes and spatial wavelengths. Nanotopography features are characterized by their height variation within an area, and are discriminated from other features of similar height by their spatial wavelength range.

NOTICE: This standard does not purport to address safety issues, if any, associated with its use. It is the responsibility of the users of this standard to establish appropriate safety and health practices and determine the applicability of regulatory or other limitations prior to use.

Purpose

This guide provides a framework for reporting of nanotopography surface features on silicon wafers.

1 Ravi, K.V., "Wafer Flatness Requirements for Future Technologies," Future Fab International (July 1999).