| 1. |
. |
JEDEC JEP152 |
|
|
2007-MAY-01 • 现用 •
DDR2 DIMM Clock Skew Measurement Procedure Using A Clock Reference Board
|
|
| 2. |
. |
JEDEC JESD79-2E |
|
|
2008-APR-01 • 现用 •
DDR2 SDRAM SPECIFICATION
|
|
| 3. |
. |
JEDEC JESD82-7A |
|
|
2004-OCT-01 • 现用 •
Definition of the SSTU32864 1.8-V Configurable Registered Buffer for DDR2 RDIMM Applications
|
|
| 4. |
. |
JEDEC JESD82-8.01 |
|
|
2004-FEB-01 • 现用 •
Standard for Definition of CU877 PLL Clock Driver for Registered DDR2 DIMM Applications
|
|
| 5. |
. |
JEDEC JESD82-9B |
|
|
2007-MAY-01 • 现用 •
Definition of the SSTU32865 Registered Buffer with Parity for 2R × 4 DDR2 RDIMM Applications
|
|
| 6. |
. |
JEDEC JESD82-10A |
|
|
2007-MAY-01 • 现用 •
Definition of the SSTU32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications
|
|
| 7. |
. |
JEDEC JESD82-11 |
|
|
2004-SEP-01 • 现用 •
Standard for Definition of CU878 PLL Clock Driver for Registered DDR2 DIMM Applications
|
|
| 8. |
. |
JEDEC JESD82-12A |
|
|
2007-APR-01 • 现用 •
Definition of the SSTU32S869 and SSTU32D869 Registered Buffer with Parity for DDR2 RDIMM Applications
|
|
| 9. |
. |
JEDEC JESD82-14A |
|
|
2006-OCT-01 • 现用 •
Definition of the SSTUB32868 1.8 V Configurable Registered Buffer with Parity for DDR2 RDIMM Applications
|
|
| 10. |
. |
JEDEC JESD82-15 |
|
|
2005-NOV-01 • 现用 •
Standard for Definition of CUA878 PLL Clock Driver for Registered DDR2 DIMM Applications
|
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