| 1. |
. |
IEC 61691-4 |
|
|
2004-OCT-01 • 现用 •
Behavioural Languages - Part 4: Verilog hardware description language-First Edition; IEEE 1364
|
|
| 2. |
. |
IEC 62142 |
|
|
2005-JUN-01 • 现用 •
Verilog register transfer level synthesis-Edition 1; IEEE 1364.1
|
|
| 3. |
. |
IEEE 1364 |
|
|
2005-JAN-01 • 现用 •
Standard Verilog Hardware Description Language-IEEE Computer Society Document
|
|
| 4. |
. |
IEEE 1364.1 |
|
|
2002-DEC-10 • 已撤销 •
Standard for Verilog Register Transfer Level Synthesis-IEEE Computer Society Document
|
|
| 5. |
. |
IEEE 61691-4 |
|
|
2004-OCT-01 • 现用 •
Behavioural languages - Part 4: Verilog hardware description language-Replaces IEEE 1364-2001; IEEE Computer Society Document; Same as IEC 61691-4
|
|
| 6. |
. |
IEEE 62142 |
|
|
2005-JUN-01 • 现用 •
Verilog register transfer level synthesis-Replaces IEEE 1364.1
|
|
| 7. |
. |
IEEE 1499 |
|
|
1998-DEC-16 • 现用 •
Standard Interface for Hardware Description Models of Electronic Components-IEEE Computer Society Document
|
|
| 8. |
. |
IEEE 1800 |
|
|
2005-NOV-08 • 现用 •
SystemVerilog Unified Hardware Design, Specification, and Verification Language-IEEE Computer Society Document
|
|
| 9. |
. |
IEEE 1801 |
|
|
2009-MAR-19 • 现用 •
Design and Verification of Low Power Integrated Circuits-IEEE Computer Society
|
|
购物车